What is the size of the new IBM chip?

The new chip operates at the 0.7 nm node (7 angstroms), making it the world's first sub-1 nanometer chip technology.

How many transistors are on the IBM sub-1nm chip?

The chip packs nearly 100 billion transistors onto a piece of silicon roughly the size of a fingernail.

What is the nanostack architecture?

Nanostack is a revolutionary 3D transistor design that vertically stacks and staggers nanosheets, allowing for different material combinations in each layer to optimize performance and power.

When will the sub-1nm chip be available for purchase?

While currently a research achievement with functioning devices, IBM aims to bring this technology to production within five years.

IBM Unveils World's First Sub-1nm Chip: 100 Billion Transistors and the Nanostack Revolution

IBM has shattered the physical limits of silicon with the world's first sub-1nm chip, packing 100 billion transistors into a fingernail-sized device using revolutionary nanostack architecture.

For two decades, the semiconductor industry has been racing toward a physical wall where shrinking transistors further becomes impossible. IBM just announced they didn't just hit that wall; they found a way around it with the world's first sub-1 nanometer chip technology.

The Breakthrough: 0.7nm and 100 Billion Transistors

On Thursday, IBM Research revealed a landmark achievement that redefines the limits of silicon scaling. The new chip operates at the 0.7 nm node (also known as 7 angstroms), a scale so small it is measured in the width of individual atoms. This isn't just a marginal improvement; it represents a fundamental shift in how chips are built.

The density of this new architecture is staggering. IBM managed to cram nearly 100 billion transistors onto a silicon piece roughly the size of a fingernail. To put that in perspective, this is almost double the transistor density of their previous 2 nm chip unveiled in 2021. This leap allows for unprecedented computing power in a microscopic footprint, solving the density problem that has plagued engineers for years.

Nanostack: Reinventing the Architecture

The secret behind this impossible density isn't just making things smaller; it's stacking them differently. IBM introduced a revolutionary transistor architecture called nanostack, the industry's first known three-dimensional, nanosheet-based design. Unlike traditional flat designs, the nanostack vertically stacks and staggers transistors using 3D sequential integration.

This 3D approach unlocks capabilities that 2D designs simply cannot match:

It allows engineers to use different material combinations within each stacked layer.
Each layer can be optimized independently for performance or power efficiency.
The design overcomes the physical limitations that stop traditional scaling at the 2 nm mark.

Jay Gambetta, IBM Fellow and Director of IBM Research, emphasized that they aren't just shrinking transistors but reinventing the entire build process to deliver dramatic gains in power and efficiency.

Diagram comparing 2D chip design to IBM's 3D nanostack architecture

Performance Gains and Energy Efficiency

Why does this matter for the devices we use and the AI systems we rely on? The technical results from IBM's testing show a massive leap in capability compared to their 2 nm predecessors. The new sub-1nm technology delivers specific, quantifiable improvements that could reshape the computing landscape.

According to published results, the chip offers:

Up to 50% more performance for compute-intensive tasks.
Up to 70% better energy efficiency, crucial for battery-powered devices and data centers.
A significant reduction in the power demands of generative AI and cloud infrastructure.

These metrics suggest that the era of "more power for less energy" is not only alive but accelerating. This efficiency is particularly vital as the world shifts toward energy-hungry AI models and next-generation electronic devices.

Extending Moore's Law for Another Decade

Skeptics have long predicted that Moore's Law—the observation that transistor counts double approximately every two years—was running out of runway. IBM's roadmap suggests otherwise. The new nanostack architecture projects at least another decade of scaling below 1 nm.

This achievement ensures that the industry can continue to innovate without hitting a hard physics wall anytime soon. By extending the viability of Moore's Law, IBM provides a clear path for future advancements in:

Generative AI and large language models.
Advanced cloud infrastructure and data centers.
Next-generation consumer electronics and critical infrastructure systems.

The research was conducted at a leading facility in Albany, New York, which will soon house an ASML-developed High-NA EUV lithography tool. Partners including Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions are already helping develop the complex processes required to bring this technology to life.

Engineer holding fingernail-sized 0.7nm chip with 100 billion transistor overlay

From Lab to Reality: The Road Ahead

While the announcement is a massive milestone, it is important to manage expectations regarding immediate availability. The sub-1nm chip is currently a research achievement with functioning devices already produced in the lab. IBM aims to move this technology into commercial production within five years.

This timeline reflects the immense complexity of moving from a proof-of-concept to mass manufacturing. However, the successful creation of functioning devices at this scale proves that the physics works. If the industry can maintain this pace, the next five years will see a rapid transition from theoretical limits to the chips that will power the future of computing.